Job Description

Education : Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or a related field.

Experience :

• Proven experience in RTL design and integration (using Verilog , VHDL , or SystemVerilog ).
• Hands-on experience with digital design verification and subsystem integration .
• Experience with quality assurance tools and processes for RTL code.
• Knowledge of front-end design flow including synthesis, linting, and static analysis.

Technical Skills :

• Strong proficiency in RTL coding languages: Verilog , VHDL , or SystemVerilog .
• Experience with EDA tools (e.g., Cadence , Synopsys , Mentor Graphics ).
• Familiarity with simulation tools (e.g., ModelSim , VCS , Xcelium ).
• Experience with debugging and troubleshooting integration issues in RTL designs.
• Strong understanding of timing analysis and timing closure .

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